Programmable analog floating gate circuits have been used since the early 1980's in applications that only require moderate absolute voltage accuracy over time, e.g., an absolute voltage accuracy of 100-200 mV over time. Such devices are conventionally used to provide long-term non-volatile storage of charge on a floating gate. A floating gate is an island of conductive material that is electrically isolated from a substrate but capacitively coupled to the substrate or to other conductive layers. Typically, a floating gate forms the gate of an MOS transistor that is used to read the level of charge on the floating gate without causing any leakage of charge therefrom.
Various means are known in the art for introducing charge onto a floating gate and for removing the charge from the floating gate. Once the floating gate has been programmed at a particular charge level, it remains at that level essentially permanently, because the floating gate is surrounded by an insulating material which acts as a barrier to discharging of the floating gate. Charge is typically coupled to the floating gate using hot electron injection or electron tunneling. Charge is typically removed from the floating gate by exposure to radiation (UV light, x-rays), avalanched injection, or Fowler-Nordheim electron tunneling. The use of electrons emitted from a cold conductor was first described in an article entitled Electron Emission in Intense Electric Fields by R. H. Fowler and Dr. L. Nordheim, Royal Soc. Proc., A, Vol. 119 (1928). Use of this phenomenon in electron tunneling through an oxide layer is described in an article entitled Fowler-Nordheim Tunneling into Thermally Grown SiO2 by M. Lenzlinger and E. H. Snow, Journal of Applied Physics, Vol. 40, No. 1 (January, 1969), both of which are incorporated herein by reference. Such analog floating gate circuits have been used, for instance, in digital nonvolatile memory devices and in analog nonvolatile circuits including voltage reference, Vcc sense, and power-on reset circuits.
FIG. 1A is a schematic diagram that illustrates one embodiment of an analog nonvolatile floating gate circuit implemented using two polysilicon layers formed on a substrate and two electron tunneling regions. FIG. 1A illustrates a cross-sectional view of an exemplary prior art programmable voltage reference circuit 70 formed on a substrate 71. Reference circuit 70 comprises a Program electrode formed from a first polysilicon layer (poly1), an Erase electrode formed from a second polysilicon layer (poly2), and an electrically isolated floating gate comprised of a poly1 layer and a poly2 layer connected together at a corner contact 76. Typically, polysilicon layers 1 and 2 are separated from each other by a thick oxide dielectric, with the floating gate fg being completely surrounded by dielectric. The floating gate fg is also the gate of an NMOS transistor TØ shown at 73, with a drain D and a source S that are heavily doped n+ regions in substrate 70, which is P type. (The number zero is also referred to as “0” or Ø herein.) The portion of dielectric between the poly1 Program electrode and the floating gate fg, as shown at 74, is a program tunnel region (or “tunnel device”) TP, and the portion of dielectric between the poly1 floating gate fg and the poly2 erase electrode, shown at 75, is an erase tunnel region TE. Both tunnel regions have a given capacitance. Since these tunnel regions 74,75 are typically formed in thick oxide dielectric, they are generally referred to as “thick oxide tunneling devices” or “enhanced emission tunneling devices.” Such thick oxide tunneling devices enable the floating gate to retain accurate analog voltages in the +/−4 volt range for many years. This relatively high analog voltage retention is made possible by the fact that the electric field in most of the thick dielectric in tunnel regions 74,75 remains very low, even when several volts are applied across the tunnel device. This low field and thick oxide provides a high barrier to charge loss until the field is high enough to cause Fowler-Nordheim tunneling to occur. Finally, reference circuit 70 includes a steering capacitor CC that is the capacitance between floating gate fg and a different n+ region formed in the substrate that is connected to a Cap electrode.
FIG. 1B is a schematic diagram that illustrates a second embodiment of a floating gate circuit 70 that is implemented using three polysilicon layers. The three polysilicon floating gate circuit 70′ is similar to the two polysilicon embodiment except that, for example Erase electrode is formed from a third polysilicon layer (poly 3). In addition, the floating gate fg is formed entirely from a poly2 layer. Thus, in this embodiment there is no need for a corner contact to be formed between the poly1 layer portion and the poly2 layer portion of floating gate fg, which is required for the two polysilicon layer cell shown in FIG. 1A.
Referring to FIG. 1C, shown at 25 is an equivalent circuit diagram for the voltage reference circuit 70 of FIG. 1A and 70′ of FIG. 1B. For simplicity, each circuit element of FIG. 1C is identically labeled with its corresponding element in FIGS. 1A and 1B.
Setting reference circuit 70 to a specific voltage level is accomplished using two separate operations. Referring again to FIG. 1A, the floating gate fg is first programmed or “reset” to an off condition. The floating gate fg is then erased or “set” to a specific voltage level. Floating gate fg is reset by programming it to a net negative voltage, which turns off transistor TØ. This programming is done by holding the Program electrode low and ramping the n+ bottom plate of the relatively large steering capacitor CC to 15 to 20V via the Cap electrode. Steering capacitor CC couples the floating gate fg high, which causes electrons to tunnel through the thick oxide at 74 from the poly1 Program electrode to the floating gate fg. This results in a net negative charge on floating gate fg. When the bottom plate of steering capacitor CC is returned to ground, this couples floating gate fg negative, i.e., below ground, which turns off the NMOS transistor TØ.
To set reference circuit 70 to a specific voltage level, the n+ bottom plate of steering capacitor CC, the Cap electrode, is held at ground while the Erase electrode is ramped to a high voltage, i.e., 12 to 20V. Tunneling of electrons from floating gate fg to the poly2 Erase electrode through the thick oxide at 75 begins when the voltage across tunnel device TE reaches a certain voltage, which is typically approximately 11V. This tunneling of electrons from the fg through tunnel device TE increases the voltage of floating gate fg. The voltage on floating gate fg then “follows” the voltage ramp coupled to the poly2 Erase electrode, but at a voltage level offset by about 11V below the voltage on the Erase electrode. When the voltage on floating gate fg reaches the desired set level, the voltage ramp on poly2 Erase electrode is stopped and then pulled back down to ground. This leaves the voltage on floating gate fg set at approximately the desired voltage level.
As indicated above, reference circuit 70 meets the requirements for voltage reference applications where approximately 200 mV accuracy is sufficient. The accuracy of circuit 70 is limited for two reasons. First, the potential on floating gate fg shifts down about 100 mV to 200 mV after it is set due to the capacitance of erase tunnel device TE which couples floating gate fg down when the poly2 Erase electrode is pulled down from a high voltage to ØV. The amount of this change depends on the ratio of the capacitance of erase tunnel device TE to the rest of the capacitance of floating gate fg (mostly due to steering capacitor CC), as well as the magnitude of the change in voltage on the poly2 Erase electrode. This voltage “offset” is well defined and predictable, but always occurs in such prior art voltage reference circuits because the capacitance of erase tunnel device TE cannot be zero. Second, the accuracy of circuit 70 is also limited because the potential of floating gate fg changes another 100 mV to 200 mV over time after it is set due to various factors, including detrapping of the tunnel devices and dielectric relaxation of all the floating gate fg capacitors.
An analog voltage reference storage device that uses a floating gate is described in U.S. Pat. No. 5,166,562 and teaches the uses of hot electron injection for injecting electrons onto the floating gate and electron tunneling for removing electrons from the floating gate. The floating gate is programmed by controlling the current of the hot electron injected electrons after an erase step has set the floating gate to an initial voltage. See also U.S. Pat. No. 4,953,928. Although this method of programming the charge on a floating gate is more accurate than earlier analog voltage reference circuits including a floating gate, the level of accuracy is still on the order of 50 mV to 200 mV.
In addition, prior art reference voltage generator circuits typically do not compensate for voltage drops due to resistances, i.e., current-resistance (IR) drops, that exist between a reference voltage generator circuit, typically in the form of an integrated circuit (IC) and a load circuit. In prior art reference voltage generator circuits, this has not been an issue because this voltage drop was negligible in comparison to the inherent inaccuracy of the voltage generated by the reference voltage generator circuit. When the required accuracy of this output voltage is much higher, in the range of ±1 mV or better, for example, the IR drop between the reference voltage generator circuit and the load circuit may contribute significantly to the amount of error in the value of the reference voltage that exists at the input terminal of the load circuit.
FIG. 2 is a simplified schematic illustrating exemplary wiring connections in an integrated circuit (IC) package 210, and from the IC package 210 to a load circuit 240. IC package 210 includes an IC chip 212 and a plurality of input/output (I/O) package pins, e.g., pins 220, 222, and 224. The IC chip includes the floating gate reference voltage generator circuit (not shown), formed thereon using known integrated circuit processing techniques. A plurality of bonding pads, e.g., pads 214, 216, and 218, are formed on the surface of the IC chip 212. These bonding pads 214, 216, and 218 are connected to the I/O package pins 220, 222, and 224 by conventional metal traces or wires 230, 232, and 234, respectively. In FIG. 2, if bonding pad 218, for example, corresponds to the voltage output terminal of the floating gate reference voltage generator circuit, there is a small first IR drop between the on-chip voltage output of the floating gate reference voltage generator circuit and bonding pad 218. There is a second IR drop along the metal trace or wire connecting bonding pad 218 to I/O package pin 224. The I/O package pin 224 is connected via a wire 242 to a load circuit 240, thereby providing a conductive path between the reference circuit and the load 240. There is a significant third IR drop along wire 242 between the I/O package pin 224 and the input terminal 244 of load 240. One or more of the above described three IR drops are not typically compensated for in the prior art. Thus, there is a voltage drop in the reference voltage supplied at the load circuit 240 due to these IR drops caused by the resistances in the conductive paths between the output of the reference voltage generator circuit and the input terminal 244 of load circuit 240.
What is needed is an analog programmable reference voltage generator circuit that compensates for the voltage drop created in the conductive path between the output terminal of the reference voltage generator circuit and the input terminal of a load, in order to provide an accurate reference voltage at the load.